1. Field of the Invention
The present invention relates to a semiconductor memory device, and, in particular, to a semiconductor memory device as a memory cell used in a static-type RAM.
2. Description of the Prior Art
The memory cell illustrated in FIG. 1 is an example of a conventional memory cell used in a static-type RAM.
The memory cell shown in FIG. 1 comprises a flip-flop (F/F) in turn comprising a pair of cross-coupled P-channel type metal-oxide semiconductors (MOS) P50, P51 and a pair of N-channel type metal-oxide semiconductors (MOS) N50, N51; and a pair of NMOSs N52, N53 comprising transfer transistors for inputting and outputting recorded data, provided with a gate terminal connected to a word line WL, and positioned between a bit line BL and a bit line BL.
The cell stability of a memory cell with this configuration is good because the F/F is formed from a CMOS. However, because this configuration uses a PMOS and an NMOS, a well region must be formed within the memory cell. Also, six MOS transistors P50, P51, N50 to N53, are required to form one memory cell. This results in a large memory cell and makes large-scale integration difficult.
There is, however, a conventional memory cell, as shown in FIG. 2, with a smaller cell size than the memory cell with the above-mentioned configuration.
The memory cell of FIG. 2, as opposed to the memory cell of FIG. 1, is a resistance load type memory cell comprising a pair of resistances R51, R52 in place of the PMOSs P50, P51 as load elements.
Because of this configuration, a well region formed within the memory cell is unnecessary, making it possible to reduce the cell size as compared with a CMOS-type memory.
Because the memory cell with this configuration is reduced in size, it is necessary to reduce the size of all the transistors, of the device spacing, and of the contacts, which is extremely difficult. In addition, the reduction of the size of the transistors causes a large substrate bias effect so that the threshold voltage of the transistors rises. For this reason, the potential of the write-in data stored at high level is comparatively low, the charge is reduced, and the soft error rate increases. Accordingly, in order to minimize such soft error rate, a large capacitance is required for a pair of inner nodes ND1, ND2 in which data is stored. Accordingly, this causes the cell size to increase.
Also, in the case where the power voltage drops as the size of the transistor is decreased, the drivability of the NMOSs N50, N51 must be large with respect to the drivability of the NMOSs N52, N53, to maintain the stability of the memory cell. Accordingly, the size of the memory cell is further increased.
In addition to the memory cell using this type of MOS transistor, as shown in FIG. 3, there is a bipolar type of SRAM cell which comprises a pair of bipolar transistors Q1, Q2, a pair of resistances R53, R54, and a pair of diodes D51, D52.
In the memory cell of this configuration, the cell size is reduced in comparison with the two above-mentioned types of memory cells, but use of the bipolar transistor causes the energy consumption to increase so that the large scale SRAM cannot be realized.
As explained above, inconveniences are introduced by using a conventional SRAM, because of the large volume requirements, including difficulties in reducing the required area in a memory cell, reduced reliability because of software errors, and high energy consumption.